1. Field of the Invention:
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a contact window over an impurity diffusion region and an electrode formed on a semiconductor substrate.
2. Description of the Prior Art:
A conventional method for fabricating a semiconductor device is described. A memory cell circuit of a static random access memory (SRAM) of CMOS type, which is one kind of a memory device, is constituted by a plurality of nMOS transistors and pMOS transistors. In a certain transistor among these transistors, it is necessary that an impurity diffusion region thereof is connected to a gate electrode of an adjacent transistor through interconnection. FIG. 4 is a plan view showing part of an example of a memory cell circuit as mentioned above. As shown in FIG. 4, a transistor has a gate electrode 6a and an impurity diffusion region 10. The impurity diffusion region 10 of this transistor is connected to a part of a gate electrode 6b of an adjacent transistor (not shown) through interconnection. Since the interconnection is made on an interlevel insulator, a contact window 15 is formed over the impurity diffusion region 10 and part of the gate electrode 6b. FIGS. 3A to 3C show a method for fabricating the contact window 15 by conventional technique. As shown in FIG. 3A, an isolation region 2 is formed on a silicon substrate 1, and an interlevel insulator 16 including insulating layers 7 and 13 is formed so as to cover the gate electrodes 6a and 6b and the impurity diffusion region 10. The thickness (m) of the interlevel insulator 16 on the impurity diffusion region 10, which should be removed so as to form the contact window 15, is different from that (1) on the gate electrodes 6a and 6b. Thus, when the contact window 15 is formed, it is necessary to etch the interlevel insulator 16 by a thickness of (1) or more. However, when the etched thickness is made (1) or more, the surface of the gate electrode 6b is partially exposed. Therefore, when an interconnection is formed after etching, the gate electrode 6b and the impurity diffusion region 10 are electrically connected to each other. Thus, the formation of the contact window 15 should be made as follows: i.e., in an opening 15a (FIG. 3B), the etched thickness should be (1) or more, and in an opening 15b (FIG. 3C), the etched thickness should be (m) or more and less than (1).
Detailed process will be described as follows. As shown in FIG. 3B, first, a resist pattern 14a having the opening 15a is formed, and the interlevel insulator 16 is etched until the surface of the gate electrode 6b is exposed. Because of this, a first contact window is formed on the gate electrode 6b. Then, as shown in FIG. 3C, a resist pattern 14b having an opening 15b is formed, and the interlevel insulator 16 is etched until the surface of the substrate 1 is exposed. Accordingly, a second contact window is formed on the impurity diffusion region 10.
As described above, according to conventional technique, the contact window 15 is formed in two steps, complicating the process.
Moreover, since an opening is formed in two steps by using different photoresists, it is necessary for the openings 15a and 15b to be designed so as to overlap each other in the region 15c in view of registration error of the lithography technique. In the case where the interlevel insulator 16 is etched using a pattern of the opening 15b after the etching using a pattern of the opening 15a, since the interlevel insulator 16 of the region 15c had already been removed, there is a problem in that the impurity diffusion region 10 of the region 15c will be subjected to significant etching damage.
Moreover, the insulating layers 7 and 13 with a total thickness of (1) are formed on the gate electrodes 6a and 6b. On the inpurity diffusion region 10, the insulating layer 13 alone is formed with a thickness of (m). When the opening 15a is formed and the etching of the interlevel insulator 16 is commenced, the interlevel insulator 16 formed on the impurity diffusion region 10 is removed before the completion of the etching of the interlevel insulator 16 on the gate electrode 6b. Thus, the isolation region 2 is also partially etched until the etching of the interlevel insulator 16 on the gate electrode 6b is completed. Because of this, there is a problem in that the thickness of the isolation region 2 is made partially thin.